- 3 minutes 39 secondsQ&A#10 RAM ParallelismHow I can parallelize a RAM in FPGA
https://surf-vhdl.com/how-to-implement-a-multi-port-memory-on-fpga/
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https://surf-vhdl.link/courses18 May 2019, 4:53 pm - 5 minutes 22 secondsep#22-Multiplier optimizationLearn how to optimize a multiplier in particular cases:
For a technical analysis go to the post:
https://surf-vhdl.link/OptimizationVhdl12b25
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https://surf-vhdl.link/courses13 May 2019, 8:01 pm - 7 minutes 23 secondsEp#21-Serial-to-Parallel Parallel-to-Serial converterLink to the post:
https://surf-vhdl.link/99990
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Music by Francis Preve - https://www.francispreve.com28 April 2019, 9:07 pm - 9 minutesQ&A#09-I need a clock!In this podcast we will understand how to connect a clock signal to our FPGA
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https://surf-vhdl.link/courses23 April 2019, 8:11 pm - 4 minutes 29 secondsQ&A#08- What is the ditheringWhat is dithering?
Where we can use this technique?
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Music by Francis Preve - https://www.francispreve.com10 April 2019, 6:42 pm - 5 minutes 33 secondsep#20-VHDL GenericVHDL Generic
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Music by Francis Preve - https://www.francispreve.com6 April 2019, 3:16 pm - 4 minutes 42 secondsEp#19-Iterative statementEven if the VHDL is not a software language, we can find a tyoica SW statement, the iterative statement. Let’s see how to use this
https://t.me/SurfVhdl/92
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Music by Francis Preve - https://www.francispreve.com22 March 2019, 10:02 pm - 7 minutes 27 secondsEp#18-the conditional assignment in VHDLLet’s understand how to implement a conditional statement in VHDL
image for the episode
http://t.me/SurfVhdl/86
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Music by Francis Preve - https://www.francispreve.com18 March 2019, 9:29 pm - 5 minutes 21 secondsep#17-waitWait Statements in VHDL
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Music by Francis Preve - https://www.francispreve.com13 March 2019, 9:35 pm - 4 minutes 3 secondsQ&A#07- What is the first thing that a recruiter does?Q&A#07- What is the first thing that a recruiter does?
When a recruiter needs to hire you as VHDL expert, what do you think he or she will do to understand if you are good for him or her?
What can you do in order to result a VHDL user?
Let’s see in this podcast.
Here you can find the feedback of my VHDL student
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https://surf-vhdl.link/courses7 March 2019, 8:55 pm - 7 minutes 16 secondsEp#16-VHDL processAnd now is time to introduce formally a Process
link to the images
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You can contact me
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Music by Francis Preve - https://www.francispreve.com6 March 2019, 10:02 pm - More Episodes? Get the App